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Senior Staff Engineer - DXIO - RTL- PCIe - SATA - Ethernet - SerDes (63301) At Advanced Micro Devices, Inc.

Location: Markham, Ontario

Job Description

What you do at AMD changes everything

At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center.

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.



The NBIO organization designs new prototypes for cutting edge design challenges AMD is facing across all market segments. The Design and Design Verification groups within this team are responsible for developing a balanced architecture between power consumption and performance, delivering high quality RTL code and creating advanced test benches using cutting edge verification techniques.

The NBIO organization has great diversity of talent from all over the globe and works with other teams around the world. You will learn from many senior team members while engaging and helping to shape the careers of newer engineers. This team is proud of its work and achievements and enjoys bringing on a new teammate to share in that success.

Distributed Cross Bar IP (DXIO) is a high-speed Internet protocol (IP) switch with distributed scheduling. Using a crossbar structure, the flow scheduling is distributed at the input buffer and at the crosspoint buffer. Each scheduler handles only local (per link) number of flows thus avoiding the need for a high processing capacity scheduler.

As a Digital Design Engineer on the DXIO team, you will be responsible for developing RTL for protocol-specific PCS such as PCIe, SATA , Ethernet etc. This is a highly technical role with challenging architectural learning opportunities and team leadership responsibilities.

What will you do?

  • Collaborate with analog design and system team to develop SerDes control algorithm.
  • Work with Physical Design team on Floor Plan, budgeting, timing closure, Signal Integrity, ECO flows, Power analysis, IO PAD placement, etc.
  • Work with global Front-End design team and physical design team for large scale ASIC chip physical implementation.
  • Perform Synthesis and netlisting tasks such as SDC Development, Scan Insertion, ECO implementation, Formal Verification, etc.
  • Serve as tech lead for approximately 2-3 junior engineers.
  • Contribute to Firmware development

What are we looking for in top candidates?

  • Have in depth knowledge of entire design process from design specification, defining architecture, micro-architecture, RTL design and functional verification, synthesis, Physical Design, Timing closure, Tape-out, and post-Si debug.
  • Some exposure to DFT is a strong plus, while expertise in Perl and Tcl is a must.
  • BS degree + 8 years; MS degree + 6 years; or PhD + 3 years experience, plus mastery of principles of logic and circuit design, software and hardware principles and methods.

#LI-DM2


Requisition Number: 63301
Country: Canada State: Ontario City: Markham
Job Function: Design

AMD welcomes and encourages applications from people with disabilities. Reasonable accommodations are available for applicants with disabilities during the recruitment process, unless undue hardship to AMD would result. Any applicant who requires accommodation should contact AskHR@amd.com

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services.